
EXAM 1 TOPICS
- Basics
- Gates: AND, OR, INVERTER, NAND, NOR
- Truth tables.
- Two-level forms: sum of products (SOP) and product of sums (POS)
- Deriving SOP and POS from truth tables.
- Normal (or cannonical) forms: SOP in which each product (AND)
term contains all input variables in either true or complemented form.
- Minterms/Maxterms
- Implementing with one gate: algebraic manipulation
- Implementing with one gate: gate equivalency rules, performing
AND/OR operations with only NAND gates or only NOR gates.
- Active high vs active low inputs and outputs.
- Changing a circuit diagram with AND/OR gates into one using
only NAND gates or only NOR gates.
- Expression Reduction Techniques.
- Algebraic reduction. Using Boolean laws and postulates (appendix A).
- Using Karnaugh Maps (you don't have to be able to explain why
Karnaugh Maps work).
- Multiplexors, demultiplexors, decoders.
- How to design multiplexors, demultiplexors, decoders.
- How to use multiplexors to implement truth tables.
- How to use decoders to implement truth tables.
- How to implement truth tables with Mux using folding.
- How to use decoders to decode addresses.
- Latches and Flip-flops.
- The S-R latch. How it works. How to implement (NOR vs NAND S-R
implementations). How to use in circuits.
- Timing diagrams and characteristic tables for the S-R latch. What
are invalid inputs and why.
- Flip-flops.
- Gated latches. How they work. Why level triggered latches are
a problem.
- Edge-triggered flip-flops. How they work, how they're implemented.
How pulse-narrowing circuits work.
- How ayschronous Preset and Clear inputs work.
- Master-slave flip-flops. How they work and are implemented.
- What a J-K flip-flop does. How to use it in a circuit.
- What a D flip-flop does, how it is implemented, how to use it in
a circuit.
- What a T flip-flop does, how it is implemented, how to use it in
a circuit.
- Memories.
- How to design and implement register files.
The differences between RAM and ROM and PLAs.
How to implement PLAs.
The difference between PROM, UVPROM, EEPROM.
The differences between Static RAM and Dynamic RAM.
How to design SRAM and DRAM using a 2D configuration with row and
column latches.
How to design SRAM and DRAM using a 2 1/2 D configuration.
How to multiplex addresses to save address pins.
How sense logic works in DRAM.
How memory banks work.
How synchronous RAM and double data rate RAM work.
Chapter 2, COD.
- Understand all of the MIPS assembly language instructions explained in chapter 3.
You will not have to write assembly language programs.
- Understand MIPS machine instructions. Know what each field in each type of
instruction is used for.
- Be able to translate between MIP's assembly language instructions and their
machine language equivalents.
- Know the different types of addressing used in MIPS assembly language and how
each of these are implemented in MIPS machine language.
- Understand how different types of branches are implemented in machine language.
- You do not have to know about alternative implementations (Intel, PowerPC, etc.)
- You do not have to know how procedure calls are implemented in MIPS.