Exam 2: April 3, 5:30 - 8:30. Open Book and Notes.

The exam will cover chapters 3, 5, and 6 of the Patterson/Hennessy book and the digital logic topics of counters and state sequencers (slides Appendix B part 8 and part 10).

Chapter 3 Arithmetic for Computers.

• Understand signed addition and subtraction. Know how to construct full adders.
• Understand how to construct an ALU and be able to modify it by adding new instructions.
• Know how to construct first and second level carry-lookahead adders.
• Understand how carry-save adders work.
• Understand and be able to implement multiplication as described in the book and in the slides.
• You are not responsible for division.
• You are not responsible for floating point arithmetic.

Chapter 5: Single-cycle and multi-cycle implementations.

• Understand the datapath and control. Be able to answer questions like 5.8-5.13 and 5.19-5.5.28 on pages 355 and 356.
• Understand finite state machines and how to design control using them. Related questions include 5.31-5.36 on pages 357-358 and 5.40-5.46 on page 359.
• You are not responsible for microcode implementations.
• Understand and be able to modify and extend the FSM and circuits for exceptions. For example, questions 5.50-5.52 on pages 359 and 360.

Chapter 5: Implementing control.

• Using finite state machines to design control.
• Using state sequencers to design control.
• Note that some of this material is in appendix C. In particular, the ALU control implementation and implementing FSM are in appendix C.

Chapter 6: pipelining.

• DataPath and Control
  • Pipeline datapath (section 6.2): stages and special hardware. Be able to do questions like 6.10 on page 455.

• Pipelined control (section 6.3): understand how control signals are created and stored.

  • Be able to look at a pipeline and identify instructions (as in questions 6.13-6.15 on pages 455 and 456).

  • If a new instruction is added (as in the chapter 5 questions), be able to describe the changes in the pipleline control.

• Data Hazards. Forwarding and Stalls (sections 6.5 and 6.5).
  • Understand how and why hazards exist. Good questions related to this are 6.17 and 6.19 on pages 456 and 457.

  • Be able to explain how forwarding works. Questions 6.18, 6.20, 6.22 on page 457.

  • Be able to construct the forwarding unit. Question 6.28, on page 457.

  • Understand how both arithmetic and load/store hazards can be solved with forwarding. Questions 6.24-6.27. on page 457.

  • Understand how branches are predicted including both the 1-bit and 2-bit schemes. Be able to implement and extend branch prediction.

  • Understand the techniques for reducing the delay of branches. Be able to implement and extend.

• Branch Hazards (section 6.6).