"CS344 PS 4"

Problem Set 4

Due: 14 February 2005

Implement the following truth table using multiplexors. Use folding to simplify your solution. Implement your solution in hdl. You must turn in circuit diagrams and equations of your solutions in addition to the .hdl file. Turn the hdl solution into the Nova/Faculty/barrj/cs344jb/Turn-In/Problem Set 4 folder. Don't forget to include the hdl file for all circuits that you use in your final solution.

A B C D F

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 0

1 1 1 1 0

Implement in hdl a 4-bit sorter circuit that sorts 4 numbers, each of 4 bits. Turn the hdl solution into the Nova/Faculty/barrj/cs344jb/Turn-In/Problem Set 4 folder. Don't forget to include the hdl file for all circuits that you use in your final solution.

Implement in hdl a register file with 4 registers each consisting of 4 bits. Your circuit must have 2 address lines, a chip select line, a load (or write) line, and 4 output lines. Turn the hdl solution into the Nova/Faculty/barrj/cs344jb/Turn-In/Problem Set 4 folder. Don't forget to include the hdl file for all circuits that you use in your final solution.

Address decoding is needed for a 4K byte memory. This memory is built from 256 X 8 chips.

How many 256 x 8 RAM chips are needed?

What size decoder is needed to fully address all 4K of memory?

Assuming the least significant address bit is A0, which address lines must be connected to the select lines on the decoder?

Assume that the 256 x 8 chips are already designed (you can use a block diagram for these). Give a circuit diagram for the 4K memory. You may assume that the decoder is already designed.

Show how a T flip-flop may be realized using a D flip-flop. You do not have to implement this in hdl.

Last updated on 15 Mar 2005 by John Barr