Implement in hdl a register file with 4 registers each
consisting of 4 bits. Your circuit must have 2 address lines, a chip
select line, a load (or write) line, and 4 output lines. Turn the hdl
solution into the Nova/Faculty/barrj/cs344jb/Turn-In/Problem Set 5
folder. Don't forget to include the
hdl file for all circuits that you use in your final solution.
The specifications of your circuit are:
Your register file must contain four registers each of which contains
four bits.
You must have a 2 bit address line. This address will be used to
select the register that will be written to or read from.
Your register file must receive a 1-bit read/write line. 0 will
indicate a read and 1 a write.
Your register file must have 4 1-bit input lines. These lines will
be used to supply the data for whichever register is selected by the
address lines.
You must have 4 data lines out. These lines will contain the
values from the selected register. Note that you do not have tri-state
gates so you may always put the contents of the selected register onto the
output lines, even if you're doing a write and not a read.
Address decoding is needed for a 4Kx8 byte memory. This memory is built
from 256 X 8 chips.
How many 256 x 8 RAM chips are needed?
What size decoder is needed to fully address all 4K of memory?
Assuming the least significant address bit is A0, which address lines
must be connected to the select lines on the decoder?
Assume that the 256 x 8 chips are already designed (you can use a
block diagram for these). Give a circuit diagram for the 4K memory. You
may assume that the decoder is already designed.
Show how a T flip-flop may be realized using a D flip-flop. You do
not have to implement this in hdl.
Memory. Assume that you want a 32M-bit memory. Also assume that you
want a 2 1/2 D memory design that minimizes the number of decoder/mux gates
and minimizes the number of pins. Just to make things interesting, also
assume that a decoder can have at most 1024 gates. Give a diagram that
shows your design. Note that you don't have to draw every component.
If components are the same (except for input/output lines) you can just
indicate how many components there are and which input/output/address/etc.
lines go to which components. You may use decoders and muxes without
showing how they're designed.
