Using J-K flip-flops and additional gating as necessary, design a
sequential circuit with an input X and an output Z such that Z is 1 only if
X has been 1 for three or more consecutive clock cycles. Show a state
diagram, a transition table, K-maps, final J-K equations, and a logic
diagram. You do not have to implement this in hdl. Hint:
You must internally count three clock pulses if X is 1. If X is 0, it
should not count.
Design a divide-by-12 counter using four J-K flip-flops. What is the
ratio of the time the output is high to the total cycle time?
Consider an 8-bit asychronous ripple counter made from J-K flip-flops.
Give the timing diagram for the change from state 127 to state 128.
Assuming 40ns delay in the flip-flops to change output, what is the delay
in changing from state 127 to 128?
What intermediate states are produced
in the change from state 127 to 128?
