Project

Spring 2001

The overall goal of this project is to design a computer system, including registers, Alu, control, and memory. The project will be done by teams in three parts. The first part is to design the memory, the second part the ALU and registers, the third part the control circuitry.

The timetable for the project is as follows:

1. Friday, 23 March. Memory done, instruction set designed.

2. Monday, 16 April. ALU and register set done.

3. Monday, 30 April. Control done.

4. Friday, 4 May. Entire project finished, printouts of the components turned in, a description of the design and instruction set turned in.

1. Exam 2 will take place the 3rd of April.

2. Spring break starts the 11th of March.

3. 4 May is the last day of classes.

4. There will be a final exam on Monday, 7 May at 7:30AM.

You will turn in the following items as part of your project on the 4th of May:

1. The LogicWorks files (including Libraries) necessary to run your design.

2. Printouts of the major components of your system.

3. A short paper (3-5 pages) that details:
   • What each person did on the project and the approximate time spent by each person on each part of the project.

   • The instruction set. You must give the instructions, their binary equivalents, and what the instructions do. Also give a chart that shows what control signals are activated by the different instructions.

   • Any known defects in your system/architecture.

   • A description of the architecture. This includes a schematic (written) of the data path and all hardware components on the datapath. You cannot just turn in printouts of your computer; you must show a stylized version of the datapath similar to those given in the book.

   • A list and description of examples that you have tested your system with.

Memory

1. You must implement a 2 1/2 D design of a 128X8 memory similar to the design given in diagram B.26 of Patterson and Hennesy or figure 3.7 of Maccabe ( Computer Systems, Arthur Maccabe, Irwin, 1993. This is the old 210 book). You may not use a mux that is larger than 8X1 or a decoder that is larger than 4X16. Your goal (that you'll be graded on) is to minimize the number of "pins" (ie, address and data lines) and to minimize the number of decoder gates.

2. You must use column latches (CAS) and row latches (RAS).

3. Your memory must accept 8 bit addressing and must store 1 byte (8 bit) words. Note that your instruction size and your CPU word may be different sizes than your memory word, but you will have to translate if they are different.

4. You may not use any of the built-in memory that is available in LogicWorks. You must create all of your memory elements from flip-flops and gates, multiplexors, and decoders. If you need additional components, check with me before you use them.

5. You must turn in the LogicWorks file containing your memory and a 2 page write up detailing the design of your circuit and what each member of the team did on the project.

6. You may work in teams of 1 or 2 for this project. You may not have any larger teams.

Architecture

1. All of the instructions given in chapter 4. These include addition, subtraction, slt, branch equal, branch not equal, jump, bitwise AND and OR, load word, and store word.

2. Your ALU must check for overflow. You will need, of course, a Zero line and a slt line.

3. Your CPU must use 8-bit (i.e., byte) or larger words. This means that 8 bits will be used to store instructions and that integers will be 8-bits. Note: You will not be able to have a three register instruction and encode all instructions with 8-bits. You will either have to use an accumulator (a register that always recieves the value from the ALU) or go to a 16-bit architecture.

4. Note that you do not have to represent floating-point numbers.

5. You may choose the size of memory and the number of general purpose registers, but must have at least 4 registers and 32 bytes of memory.

6. If you do a single cycle implementation, you must be able to read and write a register in the same cycle.

7. You may use a separate data and instruction memory.

8. Note that you will not need an ALU control unit (like shown in the book) unless your instructions have a function field.

9. You must have some way of initializing memory so that you can put a program into memory.

10. You can use absolute labels, i.e., you do not have to shift the label field in a beg or a bne instruction before calculating the new address.

11. There is also no offset in the jump instruction.

12. You may use any of the devices given in the LogicWorks libarary except you may not use RAM devices or any arithmetic devices. If you have a question, ask me before you use the device.

13. You must design your CPU so that each instruction takes a single cycle.

14. You may design and incorporate as many computational devices as you like.

15. Your design does not have to be pipelined.

16. You are encouraged to make extensive use of the device symbol facilities. Your final system should resemble figure 5.22 on page 364 of Patterson and Hennessy.

Instruction Set.

Your instruction set must include the following instructions:

1. Arithmetic: add, sub

2. Logical: and, or, ori

3. Data Transfer: lw, sw

4. Conditional Branch: beg, bne, slt

5. Unconditional Branch: j

Example Programs.

Here are two programs that should run on your computer.

y = 0;
x = a + b
while (x > 0)
{
  y = y + 1;
  x = x - 1;
}

x = a + b;
y = c - d;
if (x < y)
   z = y | x;
else
   z = x & y;