Project

Spring 2005

The overall goal of this project is to design a computer system, including registers, Alu, control, and memory. The project will be done by teams in three parts. The first part is to design the memory, the second part the ALU and registers, the third part the control circuitry.

The timetable for the project is as follows:

1. Friday, 18 March. Memory done.

2. Monday, 11 April. ALU and register set done.

3. Monday, 18 April. Instruction set designed.

4. Monday, 2 May. Control done.

5. Wednesday, 4 May. Entire project finished, printouts of the components turned in, a description of the design and instruction set turned in.

1. Exam 1 will take place Tuesday, 29 February.

2. Spring break starts the 7th of March.

3. 29 April is the last day of classes.

4. Exam 2 will take place sometime during the week of 18 April.

Memory

1. You must implement a 2 1/2 D design of a 1KX16 memory similar to the design given in the slides. You may not use a mux that is larger than 32x1 or a decoder that is larger than 5X32. Your goal (that you'll be graded on) is to minimize the number of "pins" (ie, address and data lines) and to minimize the number of decoder gates (i.e., the size of the decoder).

2. Your memory must accept 16 bit addressing and must store 2 byte (16 bit) words. Note that your instruction size and your CPU word may be different sizes than your memory word, but you will have to translate if they are different.

3. You may not use any of the built-in memory that is available in the Hardware Simulator. You must create all of your memory elements from flip-flops and gates, multiplexors, and decoders. If you need additional components, check with me before you use them. You may only use the Nand.hdl and Bit.hdl built-in chips. All other chips you must design. Of course, once you design a chip you may use that chip in other chips. In particular, you may use any chips that you have implemented for problem sets.

4. You must turn in all hdl files used to implement your memory and a 2 page write-up detailing the design of your circuit and what each member of the team did on the project. Your write-up must include circuit diagrams of all circuits used above the gate/decoder/multiplexor level.
5. You must work in teams of 2 for this project. You may not have any larger teams.
6. Deliverables You must turn in the following items for the memory project:
• The hdl file must be turned into the TurnIn folder on Nova. You must include all components that you used for your memory.
• A one to two page paper that describes your design (use circuit diagrams where useful) and a print out of the top level chip of your memory. Do not turn in print outs of other components.

ALU and Register Set

1. Your ALU must check for overflow. There is a discussion of how to detect overflow in section 3.3 of the COD book.
2. You will need, of course, a Zero line and a slt line.

3. Your ALU must use carry-lookahead, but only one level. You will get partial credit if your ALU works correctly but does not use the carry-lookahead architecture.
4. Your ALU must add 16-bit numbers.
5. Note that you do not have to represent floating-point numbers.

6. You must have at least 4 16-bit registers, but you may have more.
7. You must have two read and one write port on your register set.
8. Deliverables You must turn in the following items for the memory project:
• The hdl file must be turned into the TurnIn folder on Nova. You must include all components that you used for your ALU and register set.
• A one to two page paper that describes your design (include circuit diagrams) and a print out of the top level chip of your ALU and the top level chip of your register set. Do not turn in print outs of other components.
• A listing of all control signals.
• A diagram and explaination of your carry-lookahead unit.

Architecture

1. All of the instructions given in chapter 3 of the Patterson & Hennesy book. See the description below for details.
2. Your CPU must use 16-bit (i.e., 2 byte) or larger words. If you use 16-bit words you will use 16 bits to store instructions and 16 bits for your data.

3. You may design your CPU so that each instruction takes a single cycle or you may use a multiple-cycle design.

4. If you do a single cycle implementation, you must be able to read and write a register in the same cycle.

5. You may use a separate data and instruction memory.

6. You must have 1K byte of memory. Your memory store may be either 8-bit (with two banks) or 16-bit.

7. Note that you will not need an ALU control unit (like shown in the book) unless your instructions have a function field.

8. You must have some way of initializing memory so that you can put a program into memory.

9. You can use absolute labels, i.e., you do not have to shift the label field in a beg or a bne instruction before calculating the new address.

10. There is also no offset in the jump instruction.

11. You must create all of your devices from NAND gates and NOT gates. You may use any components that you build from these gates in other components. So if you build AND and OR gates, you may use these in other devices.

12. You may design and incorporate as many computational devices as you like.

13. Your design does not have to be pipelined. You will get extra credit if you successfully implement pipelining.

14. Your final system should resemble figure 5.24 on page 314 of Patterson and Hennessy.

15. Deliverables You must turn in the following items for the final project:
• The hdl file must be turned into the TurnIn/Final Project folder on Nova. You must include all components that you used for your CPU (including memory).
• A two-four page paper that includes the following:
• a description of your design (use circuit diagrams where useful)
• a print out of the top level chip of your datapath and control. Do not turn in print outs of other components.
• A listing of all control signals (including ALU control signals) and when they are asserted.
• The instruction set. You must give the instructions, their binary equivalents, and what the instructions do. Also give a chart that shows what control signals are activated by the different instructions.
• A copy of your FSM.
• A diagram of your datapath (without the control circuit).
• A diagram of only your control circuit.
• Any known defects/features in your system/architecture.
• A list and description of examples and scripts that you have tested your system with.

• You must provide scripts that will initialize your CPU, load the programs given below, and run the programs.
• Each member of the team must separately turn in a paragraph describing their part in the project, what other people on the team did, how much time each person worked on the project and what percentage work each person contributed.

Instruction Set.

Your instruction set must include the following instructions:

1. Arithmetic: add, sub

2. Logical: and, or, ori

3. Data Transfer: lw, sw, lui

4. Conditional Branch: beg, bne, slt

5. Unconditional Branch: j
6. Halting instruction: hlt

Example Programs.

Here are two programs that should run on your computer. Note that you'll have to translate them into your machine langauge. You must include the machine language version of these programs in your write-up.

y = 0;
x = 100
while (x > 0)
{
  y = y + 1;
  x = x - 1;
}

// try this both ways; first the way its given, then exchange the values of x and y
x = 10;
y = 20;
if (x < y)
   z = y | x;
else
   z = x & y;

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Grading for Spring '05.

• An "A" project will have everything implemented and all of the example programs running. The write up will have to be of exceptional quality. You will also have to have additional features incorporated. For example, floating point instructions, multiple clock cycles for each instruction, exceptions, piplining, etc.

  If you implement all of the features described in the Architecture, ALU, and memory sections successfully, you will recieve a 90% on your project. To receive a higher grade, you must implement other features.

• A "B" project will have the three parts of the project implemented, running, and integrated but no advanced features implemented. The documentation will have to be complete and of very high quality.

• A "C" project will have the three parts of the project implemented, running, but not integrated. Thus you will have three files, a file containing the memory, a file containing the ALU with the registers, and a file for the control circuitry, including all necessary hardware (except the ALU and register set). This will include the sign extension unit, the PC, any extra registers, any extra adders, etc. The documentation will have to be complete and thorough.

• A "D" project will have the first two projects running completely. The third project will be finished on paper, but will not be completely implemented. You will have to hand in complete documentation explaining what you accomplished and how you would finish the project.

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Using the hdl simulator

There can be a problem with big files (such as the 1K memory) where the HardwareSimulator won't load the file. A solution to this memory size problem that works for most implementations of Java:

Open the batch file "HardwareSimulator.bat" in a text editor (like notepad) and add an argument that indicates the amount of memory that you want XP to allocate to the Java virtual machine. The original batch file contains "@echo off java -classpath..." if you change it to "@echo off java -Xmx512m -classpath" XP will allocate 512MB of memory to the Java virtual machine which will be enough to load your 1K memory file. Change the 512 to whatever the max memory of your read machine (not the size of the memory that you are creating in HDL).

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Revision History

Date	Revision
21 Feb	Changed required memory size
22 Feb	Added details to memory write-up
16 Mar	Added deliverables to memory write-up
17 Mar	Added info about overflow.	Changed required word size to 16 bits.
28 Mar	Changed due-dates.
29 Mar	added simulator info.
4 Apr	added deliverables for ALU.
5 Apr	added lui instruction.
29 Apr	added deliverables.

Last updated on 07 May 2005 by John Barr