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| | Date | Lecture | Assign | Readings | |
|---|---|---|---|---|---|
| | | Week 1 | Digital Logic combinational and sequential logic |
Problem Set 1 out |
Slides Chap 1 parts 1-3 COD** App B.1 - B.3 UM*** Appendix A |
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| | | Week 2 | Digital Logic Reduction Karnaugh Maps Multiplexors/Demultiplexors Adders |
Problem Set 1 Due Problem Set 2 Out |
Slides Chap 1 parts 4-5 COD app B.5 UM Appendix A. |
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| | | Week 3 | Digital Logic: Latches and Flip-Flops Clocks Counters Memory Elements |
Problem Set 2 Due Problem Set 3 Out |
Slides Chap 1 parts 6-7 COD app B.4, B.5 |
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| | | Week 4 | Digital Logic: State Sequencers Finite State machines Timeing Methodologies |
Problem Set 3 Due Problem Set 4 Out 16 Feb: Project 1 Out |
Slides Chap 1 parts 8-9 COD app B.6, B.7 |
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| | | Week 5 | Performance, Instruction Sets MIPS instruction set |
Problem Set 4 Due Exam 1: Tues 20 February |
COD chap 1 (skim) COD chap 2 COD chap 3 (skim) |
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** COD: Computer Organization & Design, The Hardware/Software
Interface, 3rd ed. , David A. Patterson and John L. Hennessy, Morgan
Kaufmann.
*** UM: Hardware Simulator user manual
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Last updated on
17 Jan 2005
by
John
Barr
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