Problem Set 6
	Due: Friday, 23 March 2001

	1. For this problem you are to implement (on paper) an unaligned memory. Assume that a 0 on the Size signal is used to indicate a byte operation. The memory can support 8-bit and 16-bit values, so a size value of 0 will indicate access to a 8-bit value and a size value of 1 will indicate access to a 16-bit value. Show where a word would be located in your memory. Be sure to lable lines with the address or data bits they carry. Note that this is an unaligned memory organization. This means that the first byte may be stored in bank 0 or it may be stored in bank 1. For example, if size is 1 (i.e., a 16 bit input), and the address is odd, your circuit should direct the first 8 bits of the input to bank 1 and the last 8 bits of the input to bank 0. If the address was even, your circuit would direct the first 8 bits to bank 0 and the last 8 bits to bank 1. Similarly, if you are doing a read, and the address is odd, then your circuit should direct the 8 bits from bank 1 to the most significant bits of the output word and the 8 bits from bank 0 to the least significant bits of the output word. a. Give the circuits to determine the address, CS, and R/W signals to the internal memory banks. b. Assuming that the data port is justified, (i.e., that byte values are always transmitted along lines D0- D7) design a circuit that routes the data inputs/outputs of the memory banks to the correct lines of the data port. Assume that the memory is 4 bits wide and that each bank is 2 bits wide. Show your truth tables and a circuit diagrm. Note that you are not designing the individual memory banks. You are designing the circuits that direct the input bits to the correct bank and directs the output from the banks to the correct output lines.